LLM-based Hardware Development with Hierarchical IRs and End-to-End Multi-Agent Workflow

A hierarchical intermediate representation framework that decomposes complex hardware design into architectural sketches and operational specifications, enabling multi-agent LLM workflows to generate lint-clean, synthesizable RTL.

Chenyang Yin; Agasthi Haputhanthri; Aditya Anirudh Jonnalagadda; Zhenyu Bai; Yuanming Song; Saranyu Chattopadhyay; Mohammad Fadiheh; Tom Zelazny; Subhasish Mitra; Tulika Mitra· 2026· DOI 10.48550/arXiv.2608.30659

The core problem

Large language models (LLMs) have transformed software development, yet their application to complex hardware design remains limited. This gap arises from two primary factors: the scarcity of public hardware training data and the fundamentally different methodologies inherent to hardware design. Unlike software, applying LLMs to hardware requires more than direct RTL generation; the model must comprehend module boundaries, inter-module connections, and verification requirements. The authors present an LLM-based hardware development framework that addresses these challenges through hierarchical intermediate representations (IRs) and an end-to-end multi-agent workflow. The core idea is to provide an abstraction of hardware design to LLMs via two structured IRs: the Architectural Sketch, which captures module topology and interconnection, and the Operational Specification, which defines per-module functionality and interfaces. This framework decomposes complex designs into sub-modules, specifies per-block functionality, and derives how each module should be tested and verified. A multi-agent debug loop allows agents to receive error feedback and control debug details such as signals t

Innovation

The framework is evaluated on the Verilog-Eval benchmark, a standard dataset for assessing LLM-based RTL generation. The proposed approach achieves a **pass@5 rate of 95.5%**, surpassing current state-of-the-art LLM generation frameworks. This metric indicates that in five attempts, the framework produces functionally correct RTL for 95.5% of the benchmark problems. To better assess performance on complex, realistic designs, the authors introduce a new case study spanning applications from general-purpose processors to digital signal processing (DSP) systems. Experimental results indicate that such complex designs exceed the capabilities of existing approaches, whereas the proposed framework is the only one capable of producing functional end-to-end design. The generated RTL follows all industry-standard design rules, is lint-clean, functionally correct, and fully synthesizable. This demonstrates the framework's ability to handle real-world hardware design tasks that require understanding of module boundaries, inter-module connections, and verification requirements. The multi-agent debug loop contributes significantly to the high success rate by allowing agents to iteratively refin

Large language models (LLMs) have transformed software development, yet their application to complex hardware design remains limited. This gap arises from two primary factors: the scarcity of public hardware training data and the fundamentally different methodologies inherent to hardware design. Unlike software, applying LLMs to hardware requires more than direct RTL generation; the model must comprehend module boundaries, inter-module connections, and verification requirements. The authors present an LLM-based hardware development framework that addresses these challenges through hierarchical intermediate representations (IRs) and an end-to-end multi-agent workflow. The core idea is to provide an abstraction of hardware design to LLMs via two structured IRs: the Architectural Sketch, which captures module topology and interconnection, and the Operational Specification, which defines per-module functionality and interfaces. This framework decomposes complex designs into sub-modules, specifies per-block functionality, and derives how each module should be tested and verified. A multi-agent debug loop allows agents to receive error feedback and control debug details such as signals to be probed for simulation. The framework is evaluated on the Verilog-Eval benchmark, achieving a pass@5 rate of 95.5%, surpassing current state-of-the-art LLM generation frameworks. To assess performance on complex, realistic designs, the authors introduce a new case study spanning applications from general-purpose processors to digital signal processing systems. Experimental results indicate that such complex designs exceed the capabilities of existing approaches, whereas this framework is the only one capable of producing functional end-to-end design. The generated RTL follows all industry-standard design rules, is lint-clean, functionally correct, and fully synthesizable.

The proposed methodology centers on two hierarchical intermediate representations (IRs) that bridge the gap between high-level design intent and low-level RTL implementation. The first IR, the **Architectural Sketch**, captures the module topology and interconnection structure of the hardware design. It provides a graph-like abstraction where nodes represent modules and edges represent connections, enabling LLMs to reason about the overall system architecture without being overwhelmed by implementation details. The second IR, the **Operational Specification**, defines the per-module functionality and interfaces. It specifies the behavior of each module, including input/output ports, timing constraints, and functional semantics. Together, these IRs allow the framework to decompose a complex design into sub-modules, specify the per-block functionality, and derive how each module should be tested and verified.

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