Ilmu Komputer & AI editorial
Open AccessOA2026
Report for NSF Workshop on AI for Electronic Design Automation
A distilled IMRAD digest of the NSF Workshop on AI for EDA (December 10, 2024, Vancouver, NeurIPS 2024)
Deming Chen; Vijay Ganesh; Weikai Li; Y. Lin; Yong Liu; Subhasish Mitra; David Z. Pan; Ruchir Puri; Jason Cong; Yizhou Sun· IEEE Circuits and Systems Magazine· 2026· DOI 10.1109/MCAS.2026.3662307
The core problem
The NSF Workshop on AI for Electronic Design Automation (EDA) was held on December 10, 2024, in Vancouver, alongside NeurIPS 2024. It brought together experts across machine learning and EDA to examine how AI—spanning large language models (LLMs), graph neural networks (GNNs), reinforcement learning (RL), neurosymbolic methods, and more—can facilitate EDA and shorten design turnaround. The workshop was organized around four themes: (1) AI for physical synthesis and design for manufacturing (DFM), discussing challenges in physical manufacturing processes and potential AI applications; (2) AI for high-level and logic-level synthesis (HLS/LLS), covering pragma insertion, program transformation, RTL code generation, etc.; (3) AI toolbox for optimization and design, discussing frontier AI developments that could potentially be applied to EDA tasks; and (4) AI for test and verification, including LLM-assisted verification tools, ML-augmented SAT solving, security/reliability challenges, etc. The report recommends NSF to foster AI/EDA collaboration, invest in foundational AI for EDA, develop robust data infrastructures, promote scalable compute infrastructure, and invest in workforce deve
Innovation
The workshop produced a set of actionable recommendations for NSF and the broader community. Key results include: (1) foster AI/EDA collaboration across academia and industry; (2) invest in foundational AI for EDA, including LLMs, GNNs, RL, and neurosymbolic methods; (3) develop robust data infrastructures to support training and benchmarking; (4) promote scalable compute infrastructure to enable large-scale AI-driven design; and (5) invest in workforce development to democratize hardware design and enable next-generation hardware systems. The four themes yielded specific insights: AI for physical synthesis and DFM can address manufacturing process challenges; AI for HLS/LLS can automate pragma insertion, program transformation, and RTL generation; frontier AI toolboxes can be adapted for optimization and design; and AI for test and verification can enhance LLM-assisted verification, ML-augmented SAT solving, and security/reliability. These results are qualitative and strategic, intended to guide future research and funding priorities.
The NSF Workshop on AI for Electronic Design Automation (EDA) was held on December 10, 2024, in Vancouver, alongside NeurIPS 2024. It brought together experts across machine learning and EDA to examine how AI—spanning large language models (LLMs), graph neural networks (GNNs), reinforcement learning (RL), neurosymbolic methods, and more—can facilitate EDA and shorten design turnaround. The workshop was organized around four themes: (1) AI for physical synthesis and design for manufacturing (DFM), discussing challenges in physical manufacturing processes and potential AI applications; (2) AI for high-level and logic-level synthesis (HLS/LLS), covering pragma insertion, program transformation, RTL code generation, etc.; (3) AI toolbox for optimization and design, discussing frontier AI developments that could potentially be applied to EDA tasks; and (4) AI for test and verification, including LLM-assisted verification tools, ML-augmented SAT solving, security/reliability challenges, etc. The report recommends NSF to foster AI/EDA collaboration, invest in foundational AI for EDA, develop robust data infrastructures, promote scalable compute infrastructure, and invest in workforce development to democratize hardware design and enable next-generation hardware systems. Workshop information is available at https://ai4eda-workshop.github.io/.
The workshop employed a structured expert-panel format across four thematic tracks, each targeting a critical stage of the EDA flow. Theme 1 addressed physical synthesis and DFM, where AI could optimize layout, placement, routing, and manufacturing yield. Theme 2 focused on HLS/LLS, exploring AI-driven pragma insertion, program transformation, and RTL code generation to raise abstraction and reduce manual effort. Theme 3 surveyed frontier AI developments—such as LLMs, GNNs, RL, and neurosymbolic reasoning—that could be adapted to EDA optimization and design tasks. Theme 4 examined test and verification, including LLM-assisted verification tools, ML-augmented SAT solving, and security/reliability challenges. Discussions were distilled into recommendations for NSF, emphasizing collaboration, foundational AI for EDA, data infrastructures, scalable compute, and workforce development. The workshop website (https://ai4eda-workshop.github.io/) serves as a public repository of materials. The methodology is qualitative and consensus-based, synthesizing expert input rather than reporting new experimental results.
Why it matters
The workshop underscores a paradigm shift: AI is not merely a tool for EDA but a transformative force that can shorten design turnaround and democratize hardware design. The four themes map onto a typical EDA flow, suggesting a coherent agenda for AI integration. However, challenges remain: data scarcity and quality, the need for scalable compute, and the gap between AI research and EDA practice. The recommendations call for NSF to bridge these gaps through targeted funding, infrastructure, and workforce programs. The emphasis on neurosymbolic methods and ML-augmented SAT solving highlights the importance of combining learning with formal reasoning. Security and reliability are cross-cutting concerns, especially as AI-generated designs become more prevalent. The workshop’s consensus-based approach provides a roadmap, but implementation will require sustained collaboration. The potential impact includes faster time-to-market, lower design costs, and broader access to custom hardware, aligning with national priorities in semiconductors and AI.
Who should read this
CS practitioners and researchers
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