Ilmu Komputer & AI editorial
Performance Evaluation of Fast Fourier Transforms on Emerging RISC-V Hardware with Vector Extension Support
The core problem
Fast Fourier Transforms (FFTs) are fundamental to scientific computing, signal processing, and cryptography. The emergence of the RISC-V Vector Extension (RVV 1.0) offers a new open-standard vector ISA for high-performance computing. This work introduces **juFFTe**, a light-weight high-performance library for discrete Fourier transforms, and evaluates its performance on three RVV 1.0-enabled processors: the **SiFive X280**, the **X100 core of the SpacemiT K3**, and the **C920v2 core of the Sophon SG2044**. The study benchmarks juFFTe against the widely used **FFTW3** library and compares results with **AMD's Zen 5** architecture to assess the maturity of RISC-V for FFT workloads.
Key research questions:
- How effectively can FFT kernels be vectorized for RVV 1.0?
- What performance gains does juFFTe achieve over FFTW3 on RVV hardware?
- How do RVV platforms compare to established micro-architectures like AMD Zen 5?
Innovation
Comprehensive benchmarks reveal **substantial performance improvements** of juFFTe over FFTW3 on all three RVV-enabled processors. Key findings include:
- On the **SiFive X280**, juFFTe achieved speedups of up to **3.5×** over FFTW3 for large FFT sizes (e.g., ).
- On the **SpacemiT K3 (X100 core)**, speedups reached **2.8×** for multi-threaded workloads.
- On the **Sophon SG2044 (C920v2 core)**, juFFTe demonstrated **2.2×** improvement for single-threaded FFTs and **4.1×** for multi-threaded FFTs.
However, when compared to **AMD Zen 5** running FFTW3, the RVV platforms still lag. For instance, the Zen 5 system completed a -point FFT in **0.45 ms**, while the best RVV result (SiFive X280 with juFFTe) was **1.2 ms**—a **2.7×** gap. This indicates that while RVV vectorization is effective, RISC-V hardware needs further maturing to match established micro-architectures.
Table 1: Speedup of juFFTe over FFTW3 on RVV platforms (selected sizes)
| FFT Size | SiFive X280 | SpacemiT K3 | Sophon SG2044 |
|----------|-------------|-------------|---------------|
| | 2.1× | 1.9× | 1.7× |
| | 3.0× | 2.5× | 2.0×
- How effectively can FFT kernels be vectorized for RVV 1.0?
- What performance gains does juFFTe achieve over FFTW3 on RVV hardware?
- How do RVV platforms compare to established micro-architectures like AMD Zen 5?
Why it matters
The results demonstrate that **effective vectorization of performance-critical FFT kernels is achievable on RVV 1.0 hardware**. juFFTe's lightweight design and targeted optimizations yield significant gains over FFTW3, which is not fully optimized for RVV. The speedups are attributed to:
- **Efficient use of RVV intrinsics** for butterfly operations and twiddle factor multiplication.
- **Cache-aware blocking** to reduce memory latency.
- **Multi-threading** leveraging the high core counts of the Sophon SG2044.
Nevertheless, the performance gap with AMD Zen 5 highlights several challenges:
1. **Immature compiler support** for RVV 1.0, leading to suboptimal code generation.
2. **Limited vector length** (e.g., 256-bit on SiFive X280) compared to AVX-512 on Zen 5.
3. **Memory bandwidth constraints** on current RISC-V platforms.
The authors conclude that while RVV-enabled platforms show **promising results**, RISC-V needs further maturing—both in hardware and software ecosystems—to reach the performance of established micro-architectures. Future work includes optimizing for larger vector lengths and improving compiler auto-vectorization.
Mermaid diagram of performance gap factors:
Who should read this
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