Great Expectations: Benchmarking the Real-World Performance of RVV 1.0 in HPC

An IMRAD digest of the 2026 arXiv study evaluating SiFive X280, SpacemiT X60/X100/A100, and T-Head C920v2 against NVIDIA Grace

Stepan Nassyr; Prateek Chawla; Daniel Seibel; Jayesh Badwaik; Kaveh Haghighi Mood; Andreas Herten· 2026· DOI 10.48550/arXiv.2608.28097

The core problem

Following the ratification of the RISC-V Vector Extension (RVV 1.0), commercially available silicon has begun adopting the extension, prompting a reassessment of RISC-V viability for High-Performance Computing (HPC). The authors—Stepan Nassyr, Prateek Chawla, Daniel Seibel, Jayesh Badwaik, Kaveh Haghighi Mood, and Andreas Herten—revisit this question by benchmarking the latest RVV 1.0-capable hardware: SiFive X280 (Tenstorrent Blackhole), SpacemiT X60 (K1), SpacemiT X100/A100 (K3), and T-Head C920v2 (Sophon SG2044). The study positions these platforms against a state-of-the-art HPC ARM64 chip, NVIDIA Grace, to quantify real-world performance and identify remaining barriers to RISC-V adoption in HPC. The central hypothesis is that while RVV 1.0 delivers substantial improvements over scalar execution, hardware-specific implementation challenges still limit its competitiveness.

The findings show that RVV 1.0 delivers significant performance improvements over scalar execution across all tested platforms. However, the magnitude of these gains varies considerably depending on the hardware implementation. For instance, the SiFive X280 (Tenstorrent Blackhole) and SpacemiT X60 (K1) exhibit notable vectorization speedups in BLAS and FFTW, while the SpacemiT X100/A100 (K3) and T-Head C920v2 (Sophon SG2044) demonstrate different performance profiles. In synthetic workloads, STREAM results indicate memory bandwidth limitations on some platforms, and FMA throughput tests reveal disparities in vector unit utilization. Compared to NVIDIA Grace, the RVV 1.0 platforms generally lag in absolute performance, but the relative gains from vectorization are substantial. The HPL and HPCG benchmarks further highlight challenges in sustained performance and scalability. Overall, the results confirm that RVV 1.0 is a step forward, yet hardware-specific implementation challenges—such as vector length, memory subsystem design, and compiler support—remain significant hurdles.

Following the ratification of the RISC-V Vector Extension (RVV 1.0), commercially available silicon has begun adopting the extension, prompting a reassessment of RISC-V viability for High-Performance Computing (HPC). The authors—Stepan Nassyr, Prateek Chawla, Daniel Seibel, Jayesh Badwaik, Kaveh Haghighi Mood, and Andreas Herten—revisit this question by benchmarking the latest RVV 1.0-capable hardware: SiFive X280 (Tenstorrent Blackhole), SpacemiT X60 (K1), SpacemiT X100/A100 (K3), and T-Head C920v2 (Sophon SG2044). The study positions these platforms against a state-of-the-art HPC ARM64 chip, NVIDIA Grace, to quantify real-world performance and identify remaining barriers to RISC-V adoption in HPC. The central hypothesis is that while RVV 1.0 delivers substantial improvements over scalar execution, hardware-specific implementation challenges still limit its competitiveness.

The authors employ a dual benchmarking strategy: standard HPC benchmarks and synthetic workloads. Standard HPC benchmarks include BLAS (Basic Linear Algebra Subprograms), FFTW (Fastest Fourier Transform in the West), HPL (High-Performance Linpack), and HPCG (High-Performance Conjugate Gradient). Synthetic workloads comprise STREAM (memory bandwidth) and FMA (fused multiply-add) throughput tests. These are executed on the four RVV 1.0 platforms and compared to NVIDIA Grace. The evaluation focuses on measuring vectorization gains over scalar execution and identifying performance bottlenecks. The methodology is designed to capture both compute-intensive and memory-bound characteristics, providing a holistic view of each platform's capabilities. The benchmarks are chosen to reflect typical HPC workloads, ensuring relevance to real-world applications. The comparison with NVIDIA Grace establishes a baseline for state-of-the-art ARM64 performance, highlighting the gap that RISC-V must close.

The authors analyze the performance characteristics and discuss the remaining hurdles for RISC-V, including RVV, to become a mainstay in the HPC landscape. Key challenges include variability in vector length support, inefficiencies in memory hierarchies, and immature software ecosystems. The study notes that while RVV 1.0 provides a robust ISA foundation, the actual performance is heavily influenced by microarchitectural choices. For example, platforms with wider vector units and better memory bandwidth tend to perform closer to ARM64 counterparts. The discussion also emphasizes the need for optimized compilers and libraries to fully exploit RVV 1.0 capabilities. The comparison with NVIDIA Grace underscores the importance of holistic system design, not just ISA features. The authors conclude that RISC-V has made impressive strides, but achieving parity with established HPC architectures requires continued investment in both hardware and software. The paper serves as a benchmark for current RVV 1.0 performance and a roadmap for future improvements.

CS practitioners and researchers

Opening member content…